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54 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hc5513 tr909 dlc/flc slic with low power standby the hc5513 is a subscriber line interface circuit which is interchangeable with ericssons pbl3764 for distributed central of?ce applications. enhancements include immunity to circuit latch-up during hot plug and absence of false signaling in the presence of longitudinal currents. the hc5513 is fabricated in a high voltage dielectrically isolated (di) bipolar process that eliminates leakage currents and device latch-up problems normally associated with junction isolated (ji) ics. the elimination of the leakage currents results in improved circuit performance for wide temperature extremes. the latch free bene?t of the di xxprocess guarantees operation under adverse transient conditions. this process feature makes the hc5513 ideally suited for use in harsh outdoor environments. features ? di monolithic high voltage process ? programmable current feed (20ma to 60ma) ? programmable loop current detector threshold and bat- tery feed characteristics ? ground key and ring trip detection ? compatible with ericssons pbl3764 ? thermal shutdown ? on-hook transmission ? wide battery voltage range (-24v to -58v) ? low standby power ? meets tr-nwt-000057 transmission requirements ? -40 o c to 85 o c ambient temperature range applications ? digital loop carrier systems . . . . . . . . . . . . . . ? pair gain ? fiber-in-the-loop onus . . . . . . . . . . . . . . . . . . . ? pots ? wireless local loop . . . . . . . . . . . . . . . . . . . . . . . .? pabx ? hybrid fiber coax ? related literature - an9537, operation of the hc5513/26 evaluation board block diagram ordering information part number temp. range ( o c) package pkg. no. hc5513bim -40 to 85 28 ld plcc n28.45 HC5513BIP -40 to 85 22 ld pdip e22.4 ringrly dt dr tip ring hpt hpr v bat v cc v ee agnd bgnd v tx rsn e0 e1 c1 c2 det ring relay driver 4-wire interface vf signal pat h ground key detector loop current detector r dc rsg bias digital multiplexer ring trip detector 2-wire interface r d data sheet october 1998 file number 3963.10
55 absolute maximum ratings thermal information operating temperature range . . . . . . . . . . . . . . . . -40 o c to 110 o c power supply (-40 o c t a 85 o c) supply voltage v cc to gnd . . . . . . . . . . . . . . . . . . . . 0.5v to 7v supply voltage v ee to gnd. . . . . . . . . . . . . . . . . . . . . -7v to 0.5v supply voltage v bat to gnd . . . . . . . . . . . . . . . . . . . -70v to 0.5v ground voltage between agnd and bgnd . . . . . . . . . . . . . -0.3v to 0.3v relay driver ring relay supply voltage . . . . . . . . . . . . . . . . . 0v to v bat 75v ring relay current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma ring trip comparator input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v bat to 0v input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5ma to 5ma digital inputs, outputs (c1, c2, e0, e1, det) input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to v cc output voltage ( det not active) . . . . . . . . . . . . . . . . . .0v to v cc output current ( det) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma tipx and ringx terminals (-40 o c t a 85 o c) tipx or ringx voltage, continuous (referenced to gnd) .v bat to 2v tipx or ringx, pulse < 10ms, t rep > 10s . . . . . .v bat -20v to 5v tipx or ringx, pulse < 10 m s, t rep > 10s . . . . v bat -40v to 10v tipx or ringx, pulse < 250ns, t rep > 10s. . . . v bat -70v to 15v tipx or ringx current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ma esd rating human body model (per mil-std-883 method 3015.7) . . . .500v thermal resistance (typical, note 1) q ja o c/w 22 lead pdip package . . . . . . . . . . . . . . . . . . . . . . . 53 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . . 53 continuous dissipation at 70 o c 22 lead pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5w 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5w package power dissipation at 70 o c, t < 100ms, t rep > 1s 22 lead pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4w 28 lead plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4w derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 o c plastic dip package. . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mw/ o c plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mw/ o c maximum junction temperature range . . . . . . . . . -40 o c to 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . .300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . .543 transistors, 51 diodes caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. typical operating conditions these represent the conditions under which the part was developed and are suggested as guidelines. parameter conditions min typ max units case temperature -40 - 100 o c v cc with respect to agnd -40 o c to 85 o c 4.75 - 5.25 v v ee with respect to agnd -40 o c to 85 o c -5.25 - -4.75 v v bat with respect to bgnd -40 o c to 85 o c -58 - -24 v electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. parameter conditions min typ max units overload level 1% thd, z l = 600 w , (note 2, figure 1) 3.1 - - v peak longitudinal impedance (tip/ring) 0 < f < 100hz (note 3, figure 2) - 20 35 w /wire figure 1. overload level (two-wire port) figure 2. longitudinal impedance tip 27 v tx 19 ring 28 rsn 16 i dcmet r t r rx e rx r l v tro 600k w 300k w 600 w 23ma e l v t c 0 < f < 100hz v r lz t = v t /a t lz r = v r /a r 1v rms 300 w 300 w 2.16 m f tip 27 v tx 19 ring 28 rsn 16 r t r rx 600k w 300k w a t a r hc5513
56 longitudinal current limit (tip/ring) off-hook (active) no false detections, (loop current), lb > 45db (note 4, figure 3a) - - 20 ma peak /wire on-hook (standby), r l = no false detections (loop current) (note 5, figure 3b) --5ma peak /wire figure 3a. off-hook figure 3b. on-hook figure 3. longitudinal current limit off-hook longitudinal balance longitudinal to metallic ieee 455 - 1985, r lr , r lt = 368 w , 0.2khz < f < 4.0khz (note 6, figure 4) 55 70 - db longitudinal to metallic r lr , r lt = 300 w , 0.2khz < f < 4.0khz (note 6, figure 4) 55 70 - db metallic to longitudinal fcc part 68, para 68.310 0.2khz < f < 1.0khz 50 55 - db 1.0khz < f < 4.0khz (note 7) 50 55 - db longitudinal to 4-wire 0.2khz < f < 4.0khz (note 8, figure 4) 55 70 - db metallic to longitudinal r lr , r lt = 300 w , 0.2khz < f < 4.0khz (note 9, figure 5) 50 55 - db 4-wire to longitudinal 0.2khz < f < 4.0khz (note 10, figure 5) 50 55 - db figure 4. longitudinal to metallic and longitudinal to 4-wire balance figure 5. metallic to longitudinal and 4-wire to longitudinal balance electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. (continued) parameter conditions min typ max units r dc2 41.2k w r dc1 41.2k w c dc 1.5 m f e l -5v 39k w 368 w 368 w c 2.16 m f a tip 27 rsn 16 ring 28 r dc 14 det r d a r dc2 41.2k w r dc1 41.2k w c dc 1.5 m f e l -5v 39k w 368 w 368 w a tip 27 rsn 16 ring 28 r dc 14 det r d c 2.16 m f c 2.16 m f a r t r rx e l v tr 600k w 300k w c r lt r lr v tx 2.16 m f tip 27 v tx 19 ring 28 rsn 16 r t r rx e tr v l 600k w 300k w c r lt r lr e rx 300 w 300 w 2.16 m f tip 27 v tx 19 ring 28 rsn 16 hc5513
57 2-wire return loss c hp = 20nf 0.2khz to 0.5khz (note 11, figure 6) 25 - - db 0.5khz to 1.0khz (note 11, figure 6) 27 - - db 1.0khz to 3.4khz (note 11, figure 6) 23 - - db tip idle voltage active, i l = 0 --4- v standby, i l = 0 -<0- v ring idle voltage active, i l = 0 - -24 - v standby, i l = 0 - >-28 - v 4-wire transmit port (v tx ) overload level (z l > 20k w , 1% thd) (note 12, figure 7) 3.1 - - v peak output offset voltage e g = 0, z l = , (note 13, figure 7) -60 - 60 mv output impedance (guaranteed by design) 0.2khz < f < 03.4khz - 5 20 w 2- to 4-wire (metallic to v tx ) voltage gain 0.3khz < f < 03.4khz (note 14, figure 7) 0.98 1.0 1.02 v/v figure 6. two-wire return loss figure 7. overload level (4-wire transmit port), output offset voltage, 2-wire to 4-wire voltage gain and harmonic distortion 4-wire receive port (rsn) dc voltage i rsn = 0ma - 0 - v r x sum node impedance (guaranteed by design) 0.3khz < f < 3.4khz - - 20 w current gain-rsn to metallic 0.3khz < f < 3.4khz (note 15, figure 8) 980 1000 1020 ratio frequency response (off-hook) 2-wire to 4-wire 0dbm at 1.0khz, e rx = 0v 0.3khz < f < 3.4khz (note 16, figure 9) -0.2 - 0.2 db 4-wire to 2-wire 0dbm at 1.0khz, e g = 0v 0.3khz < f < 3.4khz (note 17, figure 9) -0.2 - 0.2 db 4-wire to 4-wire 0dbm at 1.0khz, e g = 0v 0.3khz < f < 3.4khz (note 18, figure 9) -0.2 - 0.2 db electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. (continued) parameter conditions min typ max units r rx v s 300k w z d r lr r t 600k w r r z in v m tip 27 v tx 19 ring 28 rsn 16 r t r rx i dcmet 600k w 300k w c e g r l v txo 600 w z l v tr 23ma 2.16 m f v tx tip 27 v tx 19 ring 28 rsn 16 hc5513
58 insertion loss 2-wire to 4-wire 0dbm, 1khz (note 19, figure 9) -0.2 - 0.2 db 4-wire to 2-wire 0dbm, 1khz (note 20, figure 9) -0.2 - 0.2 db gain tracking (ref = -10dbm, at 1.0khz) 2-wire to 4-wire -40dbm to +3dbm (note 21, figure 9) -0.1 - 0.1 db 2-wire to 4-wire -55dbm to -40dbm (note 21, figure 9) - 0.03 - db 4-wire to 2-wire -40dbm to +3dbm (note 22, figure 9) -0.1 - 0.1 db 4-wire to 2-wire -55dbm to -40dbm (note 22, figure 9) - 0.03 - db figure 8. current gain-rsn to metallic figure 9. frequency response, insertion loss, gain tracking and harmonic distortion noise idle channel noise at 2-wire c-message weighting (note 23, figure 10) - 12 - dbrnc idle channel noise at 4-wire c-message weighting (note 24, figure 10) - 12 - dbrnc harmonic distortion 2-wire to 4-wire 0dbm, 1khz (note 25, figure 7) - -65 -54 db 4-wire to 2-wire 0dbm, 0.3khz to 3.4khz (note 26, figure 9) - -65 -54 db battery feed characteristics constant loop current tolerance r dcx = 41.2k w i l = 2500/(r dc1 + r dc2 ), -40 o c to 85 o c (note 27) 0.9i l i l 1.1i l ma loop current tolerance (standby) i l = (v bat -3)/(r l +1800), -40 o c to 85 o c (note 28) 0.8i l i l 1.2i l ma open circuit voltage (v tip - v ring ) -40 o c to 85 o c, (active) 14 - 20 v electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. (continued) parameter conditions min typ max units r dc2 41.2k w r dc1 41.2k w c dc 1.5 m f r l 600 w tip 27 ring 28 r dc 14 rsn 16 r rx 300k w v rsn = 0v v rsn = -3v grx = ((v tr1 - v tr2 )(300k))/(-3)(600) where: v tr1 is the tip to ring voltage with v rsn = 0v v tr and v tr2 is the tip to ring voltage with v rsn = -3v r t r rx i dcmet 600k w 300k w c 1/ w c << r l e g r l v tx 600 w v tr e rx tip 27 v tx 19 ring 28 rsn 16 hc5513
59 loop current detector on-hook to off-hook r d = 39k w, -40 o c to 85 o c 372/r d 465/r d 558/r d ma off-hook to on-hook r d = 39k w, -40 o c to 85 o c 325/r d 405/r d 485/r d ma loop current hysteresis r d = 39k w, -40 o c to 85 o c 25/r d 60/r d 95/r d ma ground key detector tip/ring current difference - trigger (note 29, figure 11) 8 12 17 ma tip/ring current difference - reset (note 29, figure 11) 3 7 12 ma hysteresis (note 29, figure 11) 0 5 9 ma figure 10. idle channel noise figure 11. ground key detect ring trip detector (dt, dr) offset voltage source res = 0 -20 - 20 mv input bias current source res = 0 -500 - 500 na input common-mode range source res = 0 v bat +1 - 0 v input resistance source res = 0, balanced 3 - - m w ring relay driver v sat at 25ma i ol = 25ma - 1.0 1.5 v off-state leakage current v oh = 12v - - 10 m a digital inputs (e0, e1, c1, c2) input low voltage, v il 0 - 0.8 v input high voltage, v ih 2-v cc v input low current, i il : c1, c2 v il = 0.4v -200 - - m a input low current, i il : e0, e1 v il = 0.4v -100 - - m a input high current v ih = 2.4v - - 40 m a detector output ( det) output low voltage, v ol i ol = 2ma - - 0.45 v output high voltage, v oh i oh = 100 m a 2.7 - - v electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. (continued) parameter conditions min typ max units r t r rx 600k w 300k w 600 w v tr v tx r l tip 27 v tx 19 ring 28 rsn 16 tip 27 rsn 16 ring 28 r dc 14 r dc2 41.2k w r dc1 41.2k w c dc 1.5 m f det e1 = c1 = 0, c2 = 1 hc5513
60 internal pull-up resistor 10 15 20 k w power dissipation open circuit state c1 = c2 = 0 - - 23 mw on-hook, standby c1 = c2 = 1 - - 30 mw on-hook, active c1 = 0, c2 = 1, r l = high impedance - - 150 mw off-hook, active r l = 0 w - - 1.1 w r l = 300 w - - 0.75 w r l = 600 w - - 0.5 w temperature guard thermal shutdown 150 - 180 o c supply currents (v bat = -28v) i cc , on-hook open circuit state (c1, 2 = 0, 0) - - 1.5 ma standby state (c1, 2 = 1, 1) - - 1.7 ma active state (c1, 2 = 0,1) - - 5.5 ma i ee , on-hook open circuit state (c1, 2 = 0, 0) - - 0.8 ma standby state (c1, 2 = 1, 1) - - 0.8 ma active state (c1, 2 = 0, 1) - - 2.2 ma i bat , on-hook open circuit state (c1, 2 = 0, 0) - - 0.4 ma standby state (c1, 2 = 1, 1) - - 0.6 ma active state (c1, 2 = 0, 1) - - 3.9 ma psrr v cc to 2 or 4-wire port (note 30, figure 12) - 40 - db v ee to 2 or 4-wire port (note 30, figure 12) - 40 - db v bat to 2 or 4-wire port (note 30, figure 12) - 40 - db figure 12. power supply rejection ratio electrical speci?cations t a = -40 o c to 85 o c, v cc = 5v 5%, v ee = -5v 5%, v bat = -28v, agnd = bgnd = 0v, r dc1 = r dc2 = 41.2k w , r d = 39k w , r sg = , r f1 = r f2 = 0 w , c hp = 10nf, c dc = 1.5 m f, z l = 600 w , unless otherwise speci?ed. all pin number references in the ?gures refer to the 28 lead plcc package. (continued) parameter conditions min typ max units r t r rx 600k w 300k w r l v tx 600 w 100mv rms , 50hz to 4khz -48v supply 5v supply -5v supply psrr = 20 log (v tx /v in ) tip 27 v tx 19 ring 28 rsn 16 hc5513
61 circuit operation and design information the hc5513 is a current feed voltage sense s ubscriber l ine i nterface c ircuit (slic). this means that for short loop applications the slic provides a programed constant current to the tip and ring terminals while sensing the tip to ring voltage. the following discussion separates the slics operation into its dc and ac path, then follows up with additional circuit and design information. constant loop current (dc) path slic in the active mode the dc path establishes a constant loop current that ?ows out of tip and into the ring terminal. the loop current is programmed by resistors r dc1 , r dc2 and the voltage on the r dc pin (figure 13). the r dc voltage is determined by the voltage across r 1 in the saturation guard circuit. under constant current feed conditions, the voltage drop across r 1 sets the r dc voltage to -2.5v. this occurs when current ?ows through r 1 into the current source i 2 . the r dc voltage establishes a current (i rsn ) that is equal to v rdc /(r dc1 +r dc2 ). this current is then multiplied by 1000, in the loop current circuit, to become the tip and ring loop currents. for the purpose of the following discussion, the saturation guard voltage is de?ned as the maximum tip to ring voltage at which the slic can provide a constant current for a given battery and overhead voltage. for loop resistances that result in a tip to ring voltage less than the saturation guard voltage the loop current is defined as: where: i l = constant loop current. r dc1 and r dc2 = loop current programming resistors. capacitor c dc between r dc1 and r dc2 removes the vf signals from the battery feed control loop. the value of c dc is determined by equation 2: where t = 30ms. note: the minimum c dc value is obtained if r dc1 = r dc2 . figure 14 illustrates the relationship between the tip to ring voltage and the loop resistance. for a 0 w loop resistance both tip and ring are at v bat /2. as the loop resistance increases, so does the voltage differential between tip and ring. when this differential voltage becomes equal to the saturation guard voltage, the operation of the slics loop feed changes from a constant current feed to a resistive feed. the loop current in the resistive feed region is no longer constant but varies as a function of the loop resistance. hc5513 v tx r rx r dc1 r dc2 c dc rsn r dc i rsn tip ring -2.5v i ring i tip a 2 i tip i ring r sg r sg -5v loop current circuit saturation guard circuit a 1 i 1 i 2 r 1 + - + - + - + - -5v figure 13. dc loop current -5v i l 2.5v r dc1 r dc2 + ------------------------------------- - 1000 = (eq. 1) c dc t 1 r dc1 --------------- 1 r dc2 --------------- + ? ?? = (eq. 2) 0 1.2k -50 -40 -30 -20 -10 0 v bat = -48v, i l = 23ma, r sg = 21.4k w loop resistance ( w ) v tip v ring resistive feed region tip to ring voltage (v) constant current feed region saturation guard voltage saturation guard voltage figure 14. v tr vs r l hc5513
62 figure 15 shows the relationship between the saturation guard voltage, the loop current and the loop resistance. notice from figure 15 that for a loop resistance <1.2k w (r sg = 21.4k w ) the slic is operating in the constant current feed region and for resistances >1.2k w the slic is operating in the resistive feed region. operation in the resistive feed region allows long loop and off-hook transmission by keeping the tip and ring voltages off the rails. operation in this region is transparent to the customer. the saturation guard circuit (figure 13) monitors the tip to ring voltage via the transconductance amplifier a 1 . a 1 generates a current that is proportional to the tip to ring voltage difference. i 1 is internally set to sink all of a 1 s current until the tip to ring voltage exceeds 12.5v. when the tip to ring voltage exceeds 12.5v (with no r sg resistor) a 1 supplies more current than i 1 can sink. when this happens a 2 amplifies its input current by a factor of 12 and the current through r 1 becomes the difference between i 2 and the output current from a 2 . as the current from a 2 increases, the voltage across r 1 decreases and the output voltage on r dc decreases. this results in a corresponding decrease in the loop current. the r sg pin provides the ability to increase the saturation guard reference voltage beyond 12.5v. equation 3 gives the relationship between the r sg resistor value and the programmable saturation guard reference voltage: where: v sgref = saturation guard reference voltage. r sg = saturation guard programming resistor. when the saturation guard reference voltage is exceeded, the tip to ring voltage is calculated using equation 4: where: v tr = voltage differential between tip and ring. r l = loop resistance. for on-hook transmission r l = , equation 4 reduces to: the value of r sg should be calculated to allow maximum loop length operation. this requires that the saturation guard reference voltage be set as high as possible without clipping the incoming or outgoing vf signal. a voltage margin of -4v on tip and -4v on ring, for a total of -8v margin, is recommended as a general guideline. the value of r sg is calculated using equation 6: where: v bat = battery voltage. v margin = recommended value of -8v to allow a maximum overload level of 3.1v peak . for on-hook transmission, r l = , equation 6 reduces to: slic in the standby mode overall system power is saved by con?guring the slic in the standby state when not in use. in the standby state the tip and ring ampli?ers are disabled and internal resistors are connected between tip to ground and ring to v bat . this connection enables a loop current to ?ow when the phone goes off-hook. the loop current detector then detects this current and the slic is con?gured in the active mode for voice transmission. the loop current in standby state is calculated as follows: where: i l = loop current in the standby state. r l = loop resistance. v bat = battery voltage. (ac) transmission path slic in the active mode figure 16 shows a simpli?ed ac transmission model. circuit analysis yields the following design equations: 0 10 20 30 0 10 20 30 40 50 loop current (ma) tip to ring voltage (v) v bat = -24v, r sg = v bat = -48v, r sg = 21.4k w saturation guard resistive feed region constant current feed region r rsg = 21.4k w 100k w 100k w 4k w 1.5k w 2k w 700 w <400 w <1.2k w r l r l r rsg = w voltage, v tr = 38v saturation guard voltage, v tr = 13v figure 15. v tr vs i l and r l v sgref 12.5 510 5 r sg ------------------ + = (eq. 3) v tr r l 16.66 5 10 5 r sg + r l r dc1 r dc2 + () 600 + ---------------------------------------------------------------------- = (eq. 4) v tr 16.66 510 5 r sg ------------------ + = (eq. 5) r sg 510 5 v bat v margin C () 1 r dc1 r dc2 + () 600r l ------------------------------------------ - + ? ? ?? 16.66v C ------------------------------------------------------------------------------------------------------------------------------- ------------------- = (eq. 6) r sg 510 5 v bat v margin 16.66v C C ---------------------------------------------------------------------------- = (eq. 7) i l v bat 3v C r l 1800 w + ------------------------------- - ? (eq. 8) v tr v tx i m 2r f + = (eq. 9) v tx z t ---------- - v rx z rx ----------- + i m 1000 ------------ - = (eq. 10) v tr e g i m z l C = (eq. 11) hc5513
63 where: v tr = is the ac metallic voltage between tip and ring, including the voltage drop across the fuse resistors r f . v tx = is the ac metallic voltage. either at the ground referenced 4-wire side or the slic tip and ring terminals. i m = is the ac metallic current. r f = is a fuse resistor. z t = is used to set the slics 2-wire impedance. v rx = is the analog ground referenced receive signal. z rx = is used to set the 4-wire to 2-wire gain. e g = is the ac open circuit voltage. z l = is the line impedance. (ac) 2-wire impedance the ac 2-wire impedance (z tr ) is the impedance looking into the slic, including the fuse resistors, and is calculated as follows: let v rx = 0. then from equation 10 z tr is de?ned as: substituting in equation 9 for v tr substituting in equation 12 for v tx therefore equation 16 can now be used to match the slics impedance to any known line impedance (z tr ). example: calculate z t to make z tr = 600 w in series with 2.16 m f. r f = 20 w : z t = 560k w in series with 2.16nf. (ac) 2-wire to 4-wire gain the 2-wire to 4-wire gain is equal to v tx / v tr . from equations 9 and 10 with v rx = 0: (ac) 4-wire to 2-wire gain the 4-wire to 2-wire gain is equal to v tr /v rx . from equations 9, 10 and 11 with e g = 0: for applications where the 2-wire impedance (z tr , equation 15) is chosen to equal the line impedance (z l ), the expression for a 4-2 simpli?es to: (ac) 4-wire to 4-wire gain the 4-wire to 4-wire gain is equal to v tx /v rx . from equations 9, 10 and 11 with e g = 0: v tx z t i m 1000 ------------ - = (eq. 12) z tr v tr i m ----------- = (eq. 13) z tr v tx i m ---------- - 2r f i m i m ----------------------- + = (eq. 14) z tr z t 1000 ------------ - 2r f + = (eq. 15) z t 1000 z tr 2r f C () = (eq. 16) z t 1000 600 1 j w 2.16 10 6 C ----------------------------------------- 220 C + ? ?? = a 24 C v tx v tr ----------- z t 1000 z t 1000 2r f + ----------------------------------------- - == (eq. 17) a 42 C v tr v rx ----------- z t z rx ----------- C z l z t 1000 ------------ - 2r f z l ++ -------------------------------------------- == (eq. 18) a 42 C z t z rx ----------- C 1 2 -- - = (eq. 19) a 44 C v tx v rx ----------- z t z rx ----------- C z l 2r f + z t 1000 ------------ - 2r f z l ++ -------------------------------------------- == (eq. 20) v tx rsn tip ring i m z tr v tr e g v tx i m 1000 v tx z rx 1 hc5513 r f r f a = 4 + - + - + - + - z t + - v rx + - a = 250 a = 250 i m z l figure 16. simplified ac transmission circuit hc5513
64 transhybrid circuit the purpose of the transhybrid circuit is to remove the receive signal (v rx ) from the transmit signal (v tx ), thereby preventing an echo on the transmit side. this is accomplished by using an external op amp (usually part of the codec) and by the inversion of the signal from the 4-wire receive port (rsn) to the 4-wire transmit port (v tx ). figure 17 shows the transhybrid circuit. the input signal will be subtracted from the output signal if i 1 equals i 2 . node analysis yields the following equation: the value of z b is then: where v rx /v tx equals 1/ a 4-4 . therefore: example: given: r tx = 20k w , z rx = 280k w , z t = 562k w (standard value), r f = 20 w and z l = 600 w , the value of z b = 18.7k w . supervisory functions the loop current, ground key and the ring trip detector outputs are multiplexed to a single logic output pin called det. see table 1 to determine the active detector for a given logic input. for further discussion of the logic circuitry see section titled digital logic inputs. before proceeding with an explanation of the loop current detector, ground key detector and later the longitudinal impedance, it is important to understand the difference between a metallic and longitudinal loop currents. figure 18 illustrates 3 different types of loop current encountered. case 1 illustrates the metallic loop current. the de?nition of a metallic loop current is when equal currents ?ow out of tip and into ring. loop current is a metallic current. cases 2 and 3 illustrate the longitudinal loop current. the de?nition of a longitudinal loop current is a common mode current, that ?ows either out of or into tip and ring simultaneously. longitudinal currents in the on-hook state result in equal currents ?owing through the sense resistors r 1 and r 2 (figure 18). and longitudinal currents in the off- hook state result in unequal currents ?owing through the sense resistors r 1 and r 2 . notice that for case 2, longitudinal currents ?owing away from the slic, the current through r 1 is the metallic loop current plus the longitudinal current; whereas the current through r 2 is the metallic loop current minus the longitudinal current. longitudinal currents are generated when the phone line is in?uenced by magnetic ?elds (e.g., power lines). loop current detector figure 18 shows a simpli?ed schematic of the loop current and ground key detectors. the loop current detector works by sensing the metallic current ?owing through resistors r 1 and r 2 . this results in a current (i rd ) out of the transconductance ampli?er (gm 1 ) that is equal to the product of gm 1 and the metallic loop current. i rd then ?ows out the r d pin and through resistor r d to v ee . the value of i rd is equal to: the i rd current results in a voltage drop across r d that is compared to an internal 1.25v reference voltage. when the voltage drop across r d exceeds 1.25v, and the logic is con?gured for loop current detection, the det pin goes low. the hysteresis resistor r h adds an additional voltage effectively across r d , causing the on-hook to off-hook threshold to be slightly higher than the off-hook to on-hook threshold. taking into account the hysteresis voltage, the typical value of r d for the on-hook to off-hook condition is: taking into account the hysteresis voltage, the typical value of r d for the off-hook to on-hook condition is: v tx r tx ----------- v rx z b ----------- + 0 = (eq. 21) z b r C tx v rx v tx ----------- = (eq. 22) z b r tx z rx z t ----------- z t 1000 ------------ - 2r f z l ++ z l 2r f + -------------------------------------------- = (eq. 23) hc5513 v tx rsn r tx r fb codec/ filter i 1 i 2 v tx z rx z t + - z b v rx + - + - figure 17. transhybrid circuit i rd i tip i ring C 600 ----------------------------------- - i l 300 --------- - == (eq. 24) r d 465 i on hook to off C hook C -------------------------------------------------------------------------- = (eq. 25) r d 375 i off hook to on C hook C -------------------------------------------------------------------------- = (eq. 26) hc5513
65 a ?lter capacitor (c d ) in parallel with r d will improve the accuracy of the trip point in a noisy environment. the value of this capacitor is calculated using the following equation: where: t = 0.5ms. ground key detector a simplified schematic of the ground key detector is shown in figure 18. ground key, is the process in which the ring terminal is shorted to ground for the purpose of signaling an operator or seizing a phone line (between the central office and a private branch exchange). the ground key detector is activated when unequal current flow through resistors r1 and r2. this results in a current (igk) out of the transconductance amplifier (gm2) that is equal to the product of gm2 and the differential (itip - iring) loop current. if igk is less than the internal current source (i1), then diode d1 is on and the output of the ground key comparator is low. if igk is greater than the internal current source (i1), then diode d2 is on and the output of the ground key comparator is high. with the output of the ground key comparator high, and the logic configured for ground key detect, the det pin goes low. the ground key detector has a built in hysteresis of typically 5ma between its trigger and reset values. ring trip detector ring trip detection is accomplished with the internal ring trip comparator and the external circuitry shown in figure 19. the process of ring trip is initiated when the logic input pins are in the following states: e0 = 0, e1 = 1/0, c1 = 1 and c2 = 0. this logic condition connects the ring trip comparator to the det output, and causes the ringrly pin to energize the ring relay. the ring relay connects the tip and ring of the phone to the external circuitry in figure 19. when the phone is on-hook the dt pin is more positive than the dr pin and the det output is high. for off-hook conditions dr is more positive than dt and det goes low. when det goes low, indicating that the phone has gone off-hook, the slic is commanded by the logic inputs to go into the active state. in the active state, tip and ring are once again connected to the phone and normal operation ensues. figure 19 illustrates battery backed unbalanced ring injected ringing. for tip injected ringing just reverse the leads to the phone. the ringing source could also be balanced. note: the det output will toggle at 20hz because the dt input is not completely ?ltered by c rt . software can examine the duty cycle and determine if the det pin is low for more that half the time, if so the off-hook condition is indicated. longitudinal impedance the feedback loop described in figure 20(a, b) realizes the desired longitudinal impedances from tip to ground and from ring to ground. nominal longitudinal impedance is resistive and in the order of 22 w . in the presence of longitudinal currents this circuit attenuates the voltages that would otherwise appear at the tip and ring terminals, to levels well within the common mode range of the slic. in fact, longitudinal currents may exceed the programmed dc loop current without disturbing the slics vf transmission capabilities. hc5513 det r d r 2 gm 1 gm 2 gm 1 (i metallic ) r d c d v ref + - current loop v ee -5v ground key comparator gm 2 (i tip - i ring ) i rd r h i 1 d 1 d 2 i gk ring tip + - r 1 + - case 1 case 2 case 3 i metallic ? i longitudinal ? i longitudinal ? i metallic ? i longitudinal ? i longitudinal ? comparator digital multiplexer + - 1.25v + - r h figure 18. loop current and ground key detectors c d t r d ------- - = (eq. 27) tip ring hc5513 r rt v bat e rg r 3 r 4 r 2 r 1 dr dt ring trip comparator det c rt ringrly ring relay + - figure 19. ring trip circuit for battery backed ringing hc5513
66 the function of this circuit is to maintain the tip and ring voltages symmetrically around v bat /2, in the presence of longitudinal currents. the differential transconductance ampli?ers g t and g r accomplish this by sourcing or sinking the required current to maintain v c at v bat /2. when a longitudinal current is injected onto the tip and ring inputs, the voltage at v c moves from its equilibrium value v bat /2. when v c changes by the amount d v c , this change appears between the input terminals of the differential transconductance ampli?ers g t and g r . the output of g t and g r are the differential currents d i 1 and d i 2 , which in turn feed the differential inputs of current sources i t and i r respectively. i t and i r have current gains of 250 single ended and 500 differentially, thus leading to a change in i t and i r that is equal to 500( d i ) and 500( d i 2 ). the circuit shown in figure 20(b) illustrates the tip side of the longitudinal network. the advantages of a differential input current source are: improved noise since the noise due to current source 2i o is now correlated, power savings due to differential current gain and minimized offset error at the operational ampli?er inputs via the two 5k w resistors. digital logic inputs table 1 is the logic truth table for the ttl compatible logic input pins. the hc5513 has two enable inputs pins (e0, e1) and two control inputs pins (c1, c2). the enable pin e0 is used to enable or disable the det output pin. the det pin is enabled if e0 is at a logic level 0 and disabled if e0 is at a logic level 1. the enable pin e1 gates the ground key detector to the det output with a logic level 0, and gates the loop or ring trip detector to the det output with a logic level 1. a combination of the control pins c1 and c2 is used to select 1 of the 4 possible operating states. a description of each operating state and the control logic follow: open circuit state (c1 = 0, c2 = 0) in this state the slic is effectively off. all detectors and both the tip and ring line drive ampli?ers are powered down, presenting a high impedance to the line. power dissipation is at a minimum. active state (c1 = 0, c2 = 1) the tip output is capable of sourcing loop current and for open circuit conditions is about -4v from ground. the ring output is capable of sinking loop current and for open circuit conditions is about v bat + 4v. vf signal transmission is normal. the loop current and ground key detectors are both active, e0 and e1 determine which detector is gated to the det output. ringing state (c1 = 1, c2 = 0) the ring relay driver and the ring trip detector are activated. both the tip and ring line drive ampli?ers are powered down. both tip and ring are disconnected from the line via the external ring relay. standby state (c1 = 1, c2 = 1) both the tip and ring line drive amplifiers are powered down. internal resistors are connected between tip to ground and ring to v bat to allow loop current detect in an off-hook condition. the loop current and ground key detectors are both active, e0 and e1 determine which detector is gated to the det output. ac transmission circuit stability to ensure stability of the ac transmission feedback loop two compensation capacitors c tc and c rc are required. figure 21 (application circuit) illustrates their use. recommended value is 2200pf. figure 20a. figure 20b. figure 20. longitudinal impedance network tip ring v bat /2 g t g r d i 1 d i 1 d i 2 d i 2 i t i r r large r large d v t + - i long i long hc5513 i long i long d v r + - v c + - v bat /2 v c r large r large tip ring 5k w 5k w 20 w + - 2i 0 d i 1 d i 1 g t tip current source with differential inputs tip differential transconductance amplifier hc5513
67 ac-dc separation capacitor, c hp the high pass ?lter capacitor connected between pins hpt and hpr provides the separation between circuits sensing tip to ring dc conditions and circuits processing ac signals. a 10nf c hp will position the low end frequency response 3db break point at 48hz. where: where r hp = 330k w . thermal shutdown protection the hc5513s thermal shutdown protection is invoked if a fault condition on the tip or ring causes the temperature of the die to exceed 160 o c. if this happens, the slic goes into a high impedance state and will remain there until the temperature of the die cools down by about 20 o c. the slic will return back to its normal operating mode, providing the fault condition has been removed. surge voltage protection the hc5513 must be protected against surge voltages and power crosses. refer to maximum ratings tipx and ringx terminals for maximum allowable transient tip and ring voltages. the protection circuit shown in figure 21 utilizes diodes together with a clamping device to protect tip and ring against high voltage transients. positive transients on tip or ring are clamped to within a couple of volts above ground via diodes d 1 and d 2 . under normal operating conditions d 1 and d 2 are reverse biased and out of the circuit. negative transients on tip and ring are clamped to within a couple of volts below ground via diodes d 3 and d 4 with the help of a surgector. the surgector is required to block conduction through diodes d 3 and d 4 under normal operating conditions and allows negative surges to be returned to system ground. the fuse resistors (r f ) serve a dual purpose of being nondestructive power dissipaters during surge and fuses when the line in exposed to a power cross. power-up sequence the hc5513 has no required power-up sequence. this is a result of the d ielectrically i solated (di) process used in the fabrication of the part. by using the di process, care is no longer required to insure that the substrate be kept at the most negative potential as with junction isolated ics. printed circuit board layout care in the printed circuit board layout is essential for proper operation. all connections to the rsn pin should be made as close to the device pin as possible, to limit the interference that might be injected into the rsn terminal. it is good practice to surround the rsn pin with a ground plane. the analog and digital grounds should be tied together at the device. slic operating states f 3db 1 2 p r hp c hp () ---------------------------------------------------- - = (eq. 28) table 1. logic truth table e0 e1 c1 c2 slic operating state active detector det output 0000 open circuit no active detector logic level high 0001 active ground key detector ground key status 0010 ringing no active detector logic level high 0011 standby ground key detector ground key status 0100 open circuit no active detector logic level high 0101 active loop current detector loop current status 0110 ringing ring trip detector ring trip status 0111 standby loop current detector loop current status 1000 open circuit no active detector logic level high 1001 active ground key detector 1010 ringing no active detector 1011 standby ground key detector 1100 open circuit no active detector 1101 active loop current detector 1110 ringing ring trip detector 1111 standby loop current detector hc5513
68 notes 2. overload level (two-wire port) - the overload level is speci- fied at the 2-wire port (v tr0 ) with the signal source at the 4-wire receive port (e rx ). i dcmet =30 m a, increase the amplitude of e rx until 1% thd is measured at v tro . reference figure 1. 3. longitudinal impedance - the longitudinal impedance is computed using the following equations, where tip and ring voltages are referenced to ground. l zt ,l zr ,v t ,v r ,a r and a t are de?ned in figure 2. (tip) l zt = v t /a t (ring) l zr = v r /a r where: e l = 1v rms (0hz to 100hz). 4. longitudinal current limit (off-hook active) - off-hook (active, c 1 =1,c 2 = 0) longitudinal current limit is determined by increasing the amplitude of e l (figure 3a) until the 2-wire longitudinal balance drops below 45db. det pin remains low (no false detection). 5. longitudinal current limit (on-hook standby) - on-hook (active, c 1 =1,c 2 = 1) longitudinal current limit is determined by increasing the amplitude of e l (figure 3b) until the 2-wire longi- tudinal balance drops below 45db. det pin remains high (no false detection). 6. longitudinal to metallic balance - the longitudinal to metal- lic balance is computed using the following equation: blme = 20 log (e l /v tr ), where: e l and v tr are de?ned in figure 4. 7. metallic to longitudinal fcc part 68, para 68.310 - the metallic to longitudinal balance is de?ned in this spec. 8. longitudinal to four-wire balance - the longitudinal to 4-wire balance is computed using the following equation: blfe = 20 log (e l /v tx ),: e l and v tx are de?ned in figure 4. 9. metallic to longitudinal balance - the metallic to longitudinal balance is computed using the following equation: bmle = 20 log (e tr /v l ), e rx = 0 where: e tr ,v l and e rx are de?ned in figure 5. 10. four-wire to longitudinal balance - the 4-wire to longitudinal balance is computed using the following equation: bfle = 20 log (e rx /v l ), e tr = source is removed. where: e rx ,v l and e tr are de?ned in figure 5. 11. two-wire return loss - the 2-wire return loss is computed using the following equation: r = -20 log (2v m /v s ) where: z d = the desired impedance; e.g., the characteristic impedance of the line, nominally 600 w. (reference figure 6). 12. overload level (4-wire port) - the overload level is speci?ed at the 4-wire transmit port (v txo ) with the signal source (e g )at the 2-wire port, i dcmet = 23ma, z l = 20k w (reference figure 7). increase the amplitude of e g until 1% thd is measured at v txo . note that the gain from the 2-wire port to the 4-wire port is equal to 1. 13. output offset voltage - the output offset voltage is speci?ed with the following conditions: e g =0,i dcmet = 23ma, z l = and is measured at v tx .e g ,i dcmet ,v tx and z l are de?ned in figure 7. note: i dcmet is established with a series 600 w resistor between tip and ring. 14. two-wire to four-wire (metallic to v tx ) voltage gain - the 2-wire to 4-wire (metallic to v tx ) voltage gain is computed using the following equation. g 2-4 =(v tx /v tr ), e g = 0dbm0, v tx ,v tr , and e g are de?ned in figure 7. 15. current gain rsn to metallic - the current gain rsn to metallic is computed using the following equation: k=i m [(r dc1 +r dc2 )/(v rdc -v rsn )] k, i m ,r dc1 ,r dc2 , v rdc and v rsn are de?ned in figure 8. 16. two-wire to four-wire frequency response - the 2-wire to 4-wire frequency response is measured with respect to e g = 0dbm at 1.0khz, e rx =0v,i dcmet = 23ma. the frequency response is computed using the following equation: f 2-4 =20 log (v tx /v tr ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tx , v tr , and e g are de?ned in figure 9. 17. four-wire to two-wire frequency response - the 4-wire to 2-wire frequency response is measured with respect to e rx = 0dbm at 1.0khz, e g =0v,i dcmet = 23ma. the frequency response is computed using the following equation: f 4-2 =20 log (v tr /e rx ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tr and e rx are de?ned in figure 9. 18. four-wire to four-wire frequency response - the 4-wire to 4-wire frequency response is measured with respect to e rx = 0dbm at 1.0khz, e g =0v,i dcmet = 23ma. the frequency response is computed using the following equation: f 4-4 =20 log (v tx /e rx ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tx and e rx are de?ned in figure 9. 19. two-wire to four-wire insertion loss - the 2-wire to 4-wire insertion loss is measured with respect to e g = 0dbm at 1.0khz input signal, e rx =0,i dcmet = 23ma and is computed using the following equation: l 2-4 = 20 log (v tx /v tr ) where: v tx ,v tr , and e g are de?ned in figure 9. (note: the fuse resistors, r f , impact the insertion loss. the speci?ed insertion loss is for r f = 0). 20. four-wire to two-wire insertion loss - the 4-wire to 2-wire insertion loss is measured based upon e rx = 0dbm, 1.0khz input signal, e g =0,i dcmet = 23ma and is computed using the following equation: l 4-2 = 20 log (v tr /e rx ) where: v tr and e rx are de?ned in figure 9. 21. two-wire to four-wire gain tracking - the 2-wire to 4-wire gain tracking is referenced to measurements taken for e g = -10dbm, 1.0khz signal, e rx =0,i dcmet = 23ma and is computed using the following equation. g 2-4 =20 log (v tx /v tr ) vary amplitude -40dbm to +3dbm, or -55dbm to -40dbm and compare to -10dbm reading. v tx and v tr are de?ned in figure 9. 22. four-wire to two-wire gain tracking - the 4-wire to 2-wire gain tracking is referenced to measurements taken for e rx = -10dbm, 1.0khz signal, e g =0,i dcmet = 23ma and is computed using the following equation: g 4-2 =20 log (v tr /e rx ) vary amplitude -40dbm to +3dbm, or -55dbm to -40dbm and compare to -10dbm reading. v tr and e rx are defined in figure 9. the level is specified at the 4-wire receive port and referenced to a 600 w impedance level. hc5513
69 23. two-wire idle channel noise - the 2-wire idle channel noise at v tr is specified with the 2-wire port terminated in 600 w (r l ) and with the 4-wire receive port grounded (reference figure 10). 24. four-wire idle channel noise - the 4-wire idle channel noise at v tx is speci?ed with the 2-wire port terminated in 600 w (r l ). the noise specification is with respect to a 600 w impedance level at v tx . the 4-wire receive port is grounded (reference figure 10). 25. harmonic distortion (2-wire to 4-wire) - the harmonic dis- tortion is measured with the following conditions. e g = 0dbm at 1khz, i dcmet = 23ma. measurement taken at v tx . (reference figure 7). 26. harmonic distortion (4-wire to 2-wire) - the harmonic dis- tortion is measured with the following conditions. e rx = 0dbm0. vary frequency between 300hz and 3.4khz, i dcmet = 23ma. measurement taken at v tr . (reference figure 9). 27. constant loop current - the constant loop current is calcu- lated using the following equation: i l = 2500 / (r dc1 + r dc2 ) 28. standby state loop current - the standby state loop current is calculated using the following equation: i l = [|v bat | - 3] / [r l +1800], t a = 25 o c 29. ground key detector - (trigger) increase the input current to 8ma and verify that det goes low. (reset) decrease the input current from 17ma to 3ma and verify that det goes high. (hysteresis) compare difference between trigger and reset. 30. power supply rejection ratio - inject a 100mv rms signal (50hz to 4khz) on v bat ,v cc and v ee supplies. psrr is com- puted using the following equation: psrr = 20 log (v tx /v in ). v tx and v in are defined in figure 12. pin descriptions plcc pdip symbol description 1 ring sense internally connected to output of ring power amplifier. 2 7 bgnd battery ground - to be connected to zero potential. all loop current and longitudinal current flow from this ground. internally separate from agnd but it is recommended that it is connected to the same potential as agnd. 48 v cc 5v power supply. 5 9 ringrly ring relay driver output. 610 v bat battery supply voltage, -24v to -56v. 711 r sg saturation guard programming resistor pin. 8 12 e1 ttl compatible logic input. the logic state of e1 in conjunction with the logic state of c1 determines which detec- tor is gated to the det output. 9 13 e0 ttl compatible logic input. enables the det output when set to logic level zero and disables det output when set to a logic level one. 11 14 det detector output. ttl compatible logic output. a zero logic level indicates that the selected detector was triggered (see truth table for selection of ground key detector, loop current detector or the ring trip detector). the det output is an open collector with an internal pull-up of approximately 15k w to v cc . 12 15 c2 ttl compatible logic input. the logic states of c1 and c2 determine the operating states (open circuit, active, ringing or standby) of the slic. 13 16 c1 ttl compatible logic input. the logic states of c1 and c2 determine the operating states (open circuit, active, ringing or standby) of the slic. 14 17 r dc dc feed current programming resistor pin. constant current feed is programmed by resistors r dc1 and r dc2 connected in series from this pin to the receive summing node (rsn). the resistor junction point is decoupled to agnd to isolate the ac signal components. 15 18 agnd analog ground. 16 19 rsn receive summing node. the ac and dc current flowing into this pin establishes the metallic loop current that flows between tip and ring. the magnitude of the metallic loop current is 1000 times greater than the current into the rsn pin. the constant current programming resistors and the networks for program receive gain and 2-wire impedance all connect to this pin. 18 20 v ee -5v power supply. 19 21 v tx transmit audio output. this output is equivalent to the tip to ring metallic voltage. the network for programming the 2-wire input impedance connects between this pin and rsn. 20 22 hpr ring side of ac/dc separation capacitor c hp .c hp is required to properly separate the ring ac current from the dc loop current. the other end of c hp is connected to hpt. 21 1 hpt tip side of ac/dc separation capacitor c hp .c hp is required to properly separate the tip ac current from the dc loop current. the other end of c hp is connected to hpr. hc5513
70 22 2 rd loop current programming resistor. resistor r d sets the trigger level for the loop current detect circuit. a ?lter ca- pacitor c d is also connected between this pin and v ee . 23 3 dt input to ring trip comparator. ring trip detection is accomplished by connecting an external network to a comparator in the slic with inputs dt and dr. 25 4 dr input to ring trip comparator. ring trip detection is accomplished by connecting an external network to a comparator in the slic with inputs dt and dr. 26 tip sense internally connected to output of tip power ampli?er. 27 5 tipx output of tip power ampli?er. 28 6 ringx output of ring power ampli?er. 3, 10 17, 24 n/c no internal connection. pin descriptions (continued) plcc pdip symbol description pinouts hc5513 (plcc) top view hc5513 (pdip) top view r dc agnd rsn n/c v ee c2 c1 bgnd ring sense ringx tipx tip sense v cc n/c n/c dt rd hpt dr v tx hpr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v bat r sg e1 e0 ringrly det n/c 1 11 10 9 8 7 6 5 3 2 4 22 12 13 14 15 16 17 18 19 21 20 rd dt dr tipx ringx bgnd ringrly v cc v bat r sg v tx rsn agnd r dc v ee c1 c2 det e0 e1 hpt hpr hc5513
71 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com application circuit 21 hpt 22 rd 23 dt 25 dr 27 tipx 28 ringx 2 bgnd 4 v cc 5 ringrly 6 v bat 7 r sg hpr 20 v tx 19 v ee 18 rsn 16 agnd 15 r dc 14 c1 13 c2 12 det 11 e o 9 e 1 8 tip ring v bat r 3 r rt r 2 -5v r d r f1 r f2 c rc c tc ringing (v bat + 90v rms ) v bat c hp (note 32) -5v r tx r t r b r dc1 c dc r dc2 r fb codec/filter u 2 u 1 r rx - + c rt r 1 r 4 note 31 -5v r sg u1 slic (subscriber line interface circuit) hc5513 u2 combination codec/filter e.g. cd22354a or programmable codec/ filter, e.g. slac c dc 1.5 m f, 20%, 10v c hp 10nf, 20%, 100v (note 2) c rt 0.39 m f, 20%, 100v c tc , c rc 2200pf, 20%, 100v relay relay, 2c contacts, 5v or 12v coil d 1 - d 5 in4007 diode surgector sgt27s10 ptc polyswitch tr600-150 d 6 diode, 1n4454 r f1 , r f2 line resistor, 20 w , 1% match, 2 w carbon column resistor or thick film on ceramic r 1 , r 3 200k w , 5%, 1/4w r 2 910k w , 5%, 1/4w r 4 1.2m w , 5%, 1/4w r b 18.7k w ,1%, 1/4w r d 39k w , 5%, 1/4w r dc1 , r dc2 41.2k w , 5%, 1/4w r fb 20.0k w , 1%, 1/4w r rx 280k w , 1%, 1/4w r t 562k w , 1%, 1/4w r tx 20k w , 1%, 1/4w r rt 150 w , 5%, 2w r sg v bat = -28v, r sg = v bat = -48v, r sg = 21.4k w , 1/4w 5% notes: 31. it is recommended that the anodes of d 3 and d 4 be shorted to ground through a battery referenced surgector (sgt27s10). 32. to meet the specified 25db 2-wire return loss at 200hz, c hp needs to be 20nf, 20%, 100v. figure 21. application circuit +5v relay d 6 or 12v ptc ptc surgector a k g d 3 d 1 d 2 d 4 d 5 hc5513

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